4 序列检测&时序逻辑

VL25 输入序列连续的序列检测

这种题用移位寄存器是最方便的，用状态机会麻烦很多。

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input a,
    output reg match
    );
reg [7:0]seq;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
        seq <= 0;
        match <= 0;
    end else begin
        seq <= {seq[6:0],a};
        if(seq == 8"b01110001)
            match <= 1;
        else
            match <= 0;
    end
end
  
endmodule