14 Building Larger Circuits
Exams/review2015 count1k
计数到999再清零即可。
module top_module ( input clk, input reset, output reg[9:0] q); always@(posedge clk) begin if(reset) q <= "d0; else q <= (q<10"d999)?(q+1"b1):"d0; end endmodule
计数到999再清零即可。
module top_module ( input clk, input reset, output reg[9:0] q); always@(posedge clk) begin if(reset) q <= "d0; else q <= (q<10"d999)?(q+1"b1):"d0; end endmodule