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module top_module ( input clk, input reset, // Synchronous active-high reset output [3:0] q); always@(posedge clk) begin if(reset) q <= 4"d0; else q <= q + 1"b1; end endmodule
module top_module ( input clk, input reset, // Synchronous active-high reset output [3:0] q); always@(posedge clk) begin if(reset) q <= 4"d0; else q <= q + 1"b1; end endmodule