【HDLBits刷题笔记】10 Counters

Count15

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);
    always@(posedge clk)
    begin
        if(reset)
            q <= 4"d0;
        else
            q <= q + 1"b1;
    end
endmodule
hmoban主题是根据ripro二开的主题,极致后台体验,无插件,集成会员系统
自学咖网 » 10 Counters